This invention relates to a method of manufacturing a semiconductor device, and more particularly to a manufacturing technique of stabilizing an operation of writing information into each of elements which constitute a mask ROM (Read Only Memory).
In order to shorten the TAT (Turn Around Time) of a mask ROM, various techniques of ion-implanting for writing information (which is also referred to as “program write” or “ROM write”) after an Al wiring has been formed are known. Referring to FIGS. 9A to 9D, an explanation will be given of a conventional manufacturing technique.
Step 1: As seen from FIG. 9A, using the technique of thermal oxidation or CVD, a pad oxide film 72 of a silicon oxide film having a thickness of 25 nm is formed on a P-type semiconductor substrate 71. The pad oxide film 72 is formed to protect the surface of the semiconductor substrate 71.
Next, a silicon nitride film 73 which is an oxidation-resistant film is formed on the entire surface. Thereafter, lengthy stripes of openings 73a for forming element isolation films 74 are formed in the silicon nitride film 73 in a direction perpendicular to a paper face of this drawing.
Step 2: As seen from FIG. 9B, using the technique of LOCOS with the silicon nitride film 73 as a mask, the semiconductor substrate 71 is oxidized to form element isolation films 74. At this time, oxide regions invades between the semiconductor substrate 71 and silicon nitride film 73 so that bird's beaks 74a are formed. Next, the silicon nitride film 73 and pad oxide film 72 are removed, and using the technique of thermal oxidation, a gate insulated film 75 having a thickness of 14 nm to 17 nm is formed. Using the technique of CVD, a poly-Si film having a thickness of 350 nm is formed, and phosphorus is doped to form an N-type conductive film 76.
Step 3: As seen from FIG. 9C, the conductive film 76 is etched in lengthy strips in a direction orthogonal to the element isolation films 74 (it should be noted that the etched region, which is in parallel to the paper face, is not illustrated) to form gate electrodes 76a which serve as word lines. Using the gate electrodes 76a as a mask, P-type impurities such as boron are ion-implanted to form a source region and a drain region (which are not illustrated since they are formed below both ends of the gate electrode in a direction perpendicular to the paper face).
Through the process described above, memory cell transistors arranged in a matrix shape are formed. An interlayer insulating film 77 having a thickness of 500 nm of a silicon oxide film is formed on the entire surface. Al wirings 78 in lengthy strips, which serve as bit lines, are formed above the element isolation films 74, respectively in a direction perpendicular to the paper face. Until this step, the manufacturing process can be carried out irrespectively of what program should be written in the memory cell transistors. For this reason, the wafers can be previously manufactured. In this case, a silicon oxide film 79 serving as a protection film is formed on the entire surface.
Step 4: At the time when a program to be written is determined on receipt of a request from a customer, as seen from FIG. 9D, a photoresist 80 having openings 80a for writing a program for a mask ROM is formed. P type impurities such as boron are ion-implanted in the semiconductor substrate 71 immediately beneath the gate electrodes 76a from the openings 80a so that predetermined memory cell transistors are depleted. Thus, the threshold voltages of the memory cell transistors are lowered so that a ROM data is written.
However, generally, the processing accuracy of the photoresist is low, e.g. 0.5 μm. Therefore, the openings 80a formed in the photoresist 80 provide a variation of 0.5 μm. Further, as described above, the element isolation film 54 has the bird's beak and hence is thinned at its end. Therefore, where there is a variation in the openings 80a, as seen from FIG. 10, as the case may be, implanted impurity ions penetrate the bird's beak 74a to reach the semiconductor substrate 71 beneath the element isolation film 74, surrounded by circle A. Where such elements are adjacent to each other, a leak current flowing below the element isolation film 74, as indicated by arrow, occurs between the adjacent elements. This leads to poor element isolation. The improvement of the processing accuracy of the photoresist mask leads to a great increase in cost.
Further, in the semiconductor device incorporating various transistors having different withstand voltages, the thickness of the gate insulated film is set according to the various transistors. For example, where the gate insulated films having two kinds of film thicknesses are to be formed, a thick gate insulated film is once formed on the entire surface, and is etched at the area(s) where a thin gate insulated film is to be formed, and further the thin gate insulated film is formed again.
In this case, when the thick gate insulated film is etched away, the element isolation film will be shaved. During such a process, the thickness of the element isolation film at an ROM part gradually becomes thin.
In the process in which the ROM will be made later, ion-implantation for data write is executed to penetrate an interlayer insulating film, gate electrode and gate insulated film. Therefore, this must be carried out at high energy of 1 MeV to 3 MeV. The ion implantation at such high energy increases the lateral diffusion of implanted ions. This also leads to the poor element isolation as described.
Further, the apparatus for executing ion-implantation at such high energy is generally expensive, which results in an increase in cost.
For the reasons described above, in order to prevent the poor element isolation, the element isolation film must be set in a width larger than a processing limit so as to give sufficient allowance. In addition, it is difficult to thin the element isolation film, which hinders miniaturization.
In order to overcome such an inconvenience, the above technique of writing information is carried out using as a mask the metallic film (Al wiring) with higher accuracy than the photoresist.
Referring to FIG. 11, the problem in the process using such a metallic film as a mask will be explained. FIG. 11 illustrates a semiconductor device having a multiplayer wiring structure including Al wirings 78, 82 and 84.
When interlayer insulating films are etched using the photoresist (not shown) as a mask, an Al wiring 78 also serves as a mask. Therefore, as seen from FIG. 11, a part of an interlayer insulating film 77 as well as the interlayer insulating films 85, 83 and 81 on the Al wiring 78 is etched. At this time, the Al wiring 78 itself is also etched slightly. Thus, a deposit 86 is formed on the side wall of an opening 85a. As a result of analysis, it was found that the deposit 86 contains an etching gas (e.g. BCl3), carbon (C) contained in the photoresist and metallic wiring (Al), etc.
Owing to the presence of the deposit 86 on the side wall, the coverage when a passivation film 87 is deposited deteriorates (area surrounded by circle B in FIG. 11). This presents a problem in reliability such as occurrence of pin holes, attenuation of moisture resistance, etc. In addition, the sectional area of the Al wiring is also reduced so that the life of electromigration also attenuates. This is the first problem.
Further, in the process of writing information using the Al wiring as a mask, in many cases, a flattened interlayer insulating film is formed on the Al wiring 78. The flattened interlayer insulating film can be formed as shown in FIG. 12A, i.e. in such a manner that after a silicon oxide film 91 and spin-on-glass film (hereinafter referred to as SOG film) 92 have been formed, the SOG film 92 is etched back, and a silicon oxide film 93 is formed.
In this process, if a wide Al wiring 78A (having a width e.g. 15 μm or more) exists on the periphery of a random logic section and memory section, under the influence of the wide Al wiring 78A, the SOG film 92 becomes excessively thick on the periphery.
Thus, when the region to be information-written is etched to form an opening, as seen from FIG. 12B, an etching remainder 95 occurs because of the SOG film 92 thickened excessively. As a result, the diameter of the opening for writing information in the via hole or the ROM section runs short, thereby lowering the yield.
It is possible to suppress occurrence of the etching remainder by lengthening the etching quantity (time). However, in this case, the Al wiring itself serving as a mask is somewhat etched. In this case, although the deposit is formed on the side wall of the opening, it is not problematic as long as the etching quantity is set appropriately. However, in order to suppress the etching remainder, if an excessive etching quantity (time) is set, the deposit on the sidewall has an adverse effect. Owing to the presence of the deposit on the sidewall, the coverage when a passivation film is deposited deteriorates. This presents a problem in reliability such as occurrence of pin holes, attenuation of moisture resistance, etc. In addition, the sectional area of the Al wiring is also reduced so that the life of electromigration also attenuates.
For this reason, in order to suppress the occurrence of the etching remainder, the etching quantity (time) cannot be lengthened excessively. This is a second problem.